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32 Megabit CMOS SRAM
DP3S1MX32PY5
ADVANCED INFORMATION
DESCRIPTION:
The DP3S1MX32PY5 is a 1M x 32 SRAM module that utilizes the new and innovative space saving TSOP stacking technology. The module is constructed of two 1M x 16 SRAM' that are s configured as a 1M x 32. The DP3S1MX32PY5 module features high speed access times with common data inputs and outputs.
PIN 1 INDEX
PIN-OUT DIAGRAM
FEATURES:
* Organizations Available: 1M x 32 * Access Times: 10*, 12, 15, 20ns * 3.3 0.3** Volt Power Requirement * Fully Static Operation - No clock or refresh required * TTL-Compatible Inputs and Outputs * 80-Pin Surface Mount LP-Stack TM
I/O12 VDD I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BS1 CS VDD WE BS3 A19 A18 A17 A16 A15 I/O0 VDD I/O1 I/O2 VSS I/O3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
TOP VIEW
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
I/O11 VSS I/O10 I/O9 VDD I/O8 A5 A6 A7 A8 A9 BS2 OE VSS NU BS0 A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VDD I/O4
PIN NAMES
A0 - A19 I/O0 - I/O31 CS WE OE BS0 BS1 BS2 BS3 VDD VSS NU. Address Inputs Data Input/Output Stack Enable Write Enable Output Enable Byte Select I/O0 - I/O7 Byte Select I/O8 - I/O15 Byte Select I/O16 - I/O23 Byte Select I/O24 - I/O31 Power (+3.3V) Ground Not Usable
BS1 BS0 WE OE A0-A19 CS BS3 BS2
CE UB LB WE OE A0-A19 CE UB LB
FUNCTIONAL BLOCK DIAGRAM
I/O16-I/O31
* 0-70 only. ** 5% for 10ns only.
I/O0-I/O15
30A244-00 REV. B
This document contains information on a product under consideration for development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change or discontinue information on this product without prior notice.
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DP3S1MX32PY5
ADVANCED INFORMATION
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE 4
Symbol VDD VIH V IL TA Supply Voltage Input HIGH Voltage Input LOW Voltage Operating Temperature C CI Characteristic 10ns 12, 15, 20ns Min. 3.135 3.0 2.0 -0.3 2 0 -40 +25 +25 Typ. 3.3 3.3 Max. 3.465 3.6 V DD+0.33 0.8 +70 +85 Unit V V V
oC
CAPACITANCE 5: TA = 25 F = 1.0MHz C,
Symbol CADR CCE CBS CWE COE C I/O Parameter Address Input Chip Enable Byte Select Write Enable Output Enable Data Input/Output Max. 20 20 15 20 20 15 pF VIN2 = 0V Unit Condition Input Pulse Levels
AC TEST CONDITIONS
0V to 3.0V 2ns 1.5V Input Pulse Rise and Fall Times Input and Output Timing Reference Levels
OUTPUT LOAD
Load 1 2 CL 30pF 5pF Parameters Measured except tLZ, tHZ, tOHZ, tOLZ, and tWHZ tLZ, tHZ, tOHZ, tOLZ, and tWHZ
DC OUTPUT CHARACTERISTICS
Symbol VOH V OL Parameter HIGH Voltage LOW Voltage Conditions IOH = -2mA IOL = +2mA Min. 2.4 0.4 Max. Unit V V
Figure 1. Output Load
* Including Probe and Jig Capacitance.
+3.3V
1200
ABSOLUTE MAXIMUM RATINGS 4
Symbol TSTC TBIAS VDD VI/O Parameter Storage Temperature Temperature Under Bias Supply Voltage 1 Input/Output Voltage 1 Value -55 to +125 -55 to +125 -0.5 to +4.6 -0.5 to +4.6 Unit C C V V
DOUT CL* 780
DC OPERATING CHARACTERISTICS: Over operating ranges
Symb ol
Characteristics Input Leakage Current Output Leakage Current Dynamic Operating Current Full Standby Supply Current (CMOS) Standby Current (TTL) Output Low Voltage Output High Voltage
Test Conditions VIN = 0V to V DD, VDD = max. VI/O = 0V to V DD, VDD = max., CE = VIH CE = VIL, VDD = max., IOUT = 0mA, f = f max. f = 0, VIN VDD -0.2V or VIN VSS +0.2V, CE VDD -0.2V CE = VIH, f = f max. IOUT = +2.0mA IOUT = -2.0mA
Min. -2 -1
Max. +2 +1 900 8 210 0.4
Unit A A mA mA mA V V
30A244-00 REV. B
IIN I OUT ICC ISB1 ISB2 VOL VOH
2.4
2
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Dense-Pac Microsystems, Inc.
ADVANCED INFORMATION
DP3S1MX32PY5
TRUTH TABLE
Mode CS OE WE BS0 L H L L L L H L L L X H X BS1 L L H L L L L H L L X H X BS2 L L L H L L L L H L X H X BS3 L L L L H L L L L H X H X I/O0I/O7 DOUT High-Z DOUT DOUT DOUT DIN High-Z DIN DIN DIN High-Z High-Z High-Z I/O8I/O15 DOUT DOUT High-Z DOUT DOUT DIN DIN High-Z DIN DIN High-Z High-Z High-Z I/O16I/O23 DOUT D OUT D OUT High-Z DOUT DIN DIN DIN High-Z DIN High-Z High-Z High-Z I/O24I/O31 DOUT DOUT DOUT DOUT High-Z DIN DIN DIN DIN High-Z High-Z High-Z High-Z Supply Current
Read
L
L
H
Active
Write
L
X
L
Active
Output Data Standby
H = HIGH
L L H
L = LOW
H X X
H X X
Active Standby
X = Don' Care t
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. 1 2 3 4 5 6 7 8 9 10 11 12 Symbol tRC tAA tCO tOE tBA tLZ t OLZ t BLZ tHZ t OHZ tBHZ tOH Parameter Read Cycle Time Address Access Time CE to Output Valid Output Enable to Output Valid Byte Enable Access Time CE to Output in LOW-Z 5, 6 Output Enable to Output in LOW-Z 5, 6 Byte Enable to Output in LOW-Z CE to Output in HIGH-Z 5, 6 Output Enable to Output in HIGH-Z 5, 6 Byte Enable to Output in HIGH-Z Output Hold from Address Change 10ns
Min. Max. Min.
12ns
Max. Min.
15ns
Max.
20ns
Min. Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
10 10 10 5 5 3 1 1 6 6 6 3
12 12 12 6 6 3 1 1 7 7 7 3
15 15 15 8 8 3 1 1 8 8 8 3
20 20 20 9 9 3 1 1 9 9 9 3
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 7, 8: Over operating ranges
No. 13 14 15 16 17 18 19 20 21 22 23 Symbol tWC t AW tCW t BW tAS t WP tWR tWHZ tDW tDH t OW Parameter Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Byte Enable to End of Write Address Set-Up Time * Write Pulse Width (OE High) Write Recovery Time, CE, WE Write Enable to Output in HIGH-Z 5, 6 Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 10ns
Min. Max. Min.
12ns
Max. Min.
15ns
Max. Min.
20ns
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns
10 8.5 8.5 8.5 0 7 0 6 6 0 1
12 9 9 9 0 8 0 7 7 0 1
15 11 11 11 0 10 0 8 8 0 1
20 15 15 15 0 12 0 10 10 0 1
* Valid for both Read and Write Cycles. 30A244-00 REV. B
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DP3S1MX32PY5
ADVANCED INFORMATION
Dense-Pac Microsystems, Inc.
READ CYCLE
ADDRESS
CE
OE
BS0 - BS3
DATA OUT
WRITE CYCLE 1: WE Controlled.
ADDRESS
WE
CE
BS0 - BS3
DATA IN
DATA OUT
4
30A244-00 REV. B
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Dense-Pac Microsystems, Inc.
ADVANCED INFORMATION
DP3S1MX32PY5
WRITE CYCLE 2: CE Controlled.
ADDRESS
WE
CE
BS0 - BS3
DATA IN
DATA OUT
WRITE CYCLE 3: UB, LB Controlled.
ADDRESS
WE
CE
BS0 - BS3
DATA IN
DATA OUT
30A244-00 REV. B
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DP3S1MX32PY5
ADVANCED INFORMATION
Dense-Pac Microsystems, Inc.
ORDERING INFORMATION
DP
PREFIX
3S
TYPE
1M
MEMORY DEPTH
X
DESIG
32
MEMORY WIDTH
P
DESIG
Y5
PACKAGE
- nn
SPEED
C
GRADE C CI 10 12 15 20 COMMERCIAL COMMERCIAL PROCESSEDINDUSTRIAL TEMPERATURE 10ns 12ns 15ns 20ns 0C to +70C -40C to +85C
80-PIN LP-STACK 16 MEG BASED DEVICES MEMORY MODULE WITHOUT SUPPORT LOGIC 3.3 VOLT CMOS SRAM
NOTES: 1. All voltages are with respect to VSS. 2. -1.5V min. (Pulse Width 4ns) for I 20mA. 3. VIH (max.)=VDD+1.5Vdc (Pulse Width 4ns) for I 20mA. 4. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
5. This parameter is guaranteed and not 100% tested. 6. Transition is measured at the point of 500mV from steady state 7. 7. 9.
voltage. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite phase to the outputs must not be applied. The outputs are in a high impedance state when WE is LOW. Chip Enable and Write Enable can initiate and terminate WRITE Cycle.
MECHANICAL DRAWING
PIN 1 INDEX
.0325 [.83] (X2)
.0315 [.80] BSC
.020 [.51] .975.010 [24.77.25]
.0375 [.95] (X2) .502.010 [12.75.25] .150 MAX. [3.81 MAX.] .0315 [.80] BSC .020 [.51]
.078 [1.98] (X4)
7321 lincoln way, garden grove, california 92841-1431 * (714) 898-0007 * (800) 642-4477 * fax: (714) 897-1772 * http://www.dense-pac.com
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30A244-00 REV. B

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